Solid-state image sensors are used in, for example, video cameras, and are presently realized in a number of forms including charge coupled devices (CCDs) and CMOS image sensors. These image sensors are based on a two dimensional array of pixels. Each pixel includes a sensing element that is capable of converting a portion of an optical image into an electronic signal. These electronic signals are then used to regenerate the optical image on, for example, a liquid crystal display (LCD).
More recently, however, CMOS image sensors have gained in popularity. Pure CMOS image sensors have benefited from advances in CMOS technology for microprocessors and ASICs and provide several advantages over CCD imagers. Shrinking lithography, coupled with advanced signal-processing algorithms, sets the stage for sensor array, array control, and image processing on one chip produced using these well-established CMOS techniques. Shrinking lithography should also decrease image-array cost due to smaller pixels. However, pixels cannot shrink too much, or they have an insufficient light-sensitive area. Nonetheless, shrinking lithography provides reduced metal-line widths that connect transistors and buses in the array.
CMOS image sensors utilize either a rolling shutter (RS) methodology or a global shutter (GS) methodology to capture image data (i.e., to expose the image sensor's pixel array to light from a subject image to be captured). The rolling shutter methodology captures the image on a row-by-row basis (i.e., the image portion applied on a given pixel row is converted to captured charges by the corresponding photodiodes, the captured charges are transferred to floating diffusion nodes and then read out by way of column lines, and then the process is repeated for the next sequential pixel row). In the resulting image data, the captured charges from each row represent the subject image at a different time, so the rolling shutter methodology is non-optimal for capturing highly dynamic events (e.g., high-speed objects). In contrast, the GS methodology involves causing every pixel in a pixel array to capture associated portions of a subject image at the same time, thereby facilitating the capture of highly dynamic events. The captured image is then read out of the pixels, typically in a row-by-row fashion using a rolling shutter (RS) readout operation.
An exemplary general GS pixel arrangement for a CMOS image sensor is disclosed in U.S. Pat. No. 8,138,531 to J. W. Adkisson (2012), and includes five transistors and a floating diffusion (FD) that stores the captured image (charge) information until it is read out during a RS readout operation. That is, the image information (captured charge) generated in the photodiode of each GS pixel is transferred to and temporarily stored in the FD of each GS pixel, and then the captured charges are systematically (e.g., row by row) read out of the FD of each pixel (e.g., one row of pixels at a time) during the RS operation.
The general 5T GS pixel approach and similar approaches encounter problems including signal noise and charge generation during readout. As mentioned above, captured light signals (electrons) are transferred to the FDs in all the pixels in the array at the same time, and then the captured signals stored in the FDs are read out row-by-row. The readout sequence performed on a selected row (which is sequentially repeated for all of the rows in the array) includes (a) reading the captured signals stored on all of the FDs in the selected row (i.e., by coupling the captured signals to a column line and reading the column line), (b) resetting the FDs in the selected row (i.e., evacuating electrons from the FDs until a Dark\Reset level is achieved), and then (c) reading the reset level stored on all of the FDs in the selected row (for comparison with the captured signal). Because the reset level is not the same level that was used to transfer the electrons, there is noise associated with it. The charge generation problem arises because the general GS pixel arrangement requires storage of the captured signals in the FDs of different rows for different amounts of time—i.e., when captured signals are sequentially read out starting with an uppermost row and ending with a lowermost row, the captured signals stored in the uppermost (i.e., first-read) row are stored for a shorter amount of time than the captured signals stored in the lower rows of the array, with the captured signals in the lowermost row being stored the longest amount of time. The lower rows, especially when not illuminated (i.e., when exposed to a relatively dark portion of a captured image), will suffer from parasitic charge generation due to a contact in the FD (storage) node which strongly increases generation, thereby corrupting the captured image. This charge generation problem is one of the main incentives for providing GS image sensors with the fastest possible readout process.
One approach used to reduce readout noise in GS image sensors includes providing each GS pixel with an additional storage node (referred to herein as a memory node (MN)), and reading out the captured charge using a correlated double sampling (CDS) readout operation. U.S. Pat. No. 7,361,877 to R. D. McGrath (2006) discloses an exemplary GS pixel utilizing a pinned photodiode, two storage nodes and two transfer gates, where the first transfer gate is used to transfer a captured charge from a pinned photodiode (first pinned diode) to a MN (second pinned diode), and the second transfer gate transfers the captured charge from the MN to a FD (sense node) during the RS operation. The CDS readout operation is perform by first resetting the FD and reading the reset level (typically referred to as a sample-and-hold reset (SHR) signal value), and then transferring the captured charge from the pixel's MN to the pixel's FD, and then reading the image bit level generated by the captured charge (typically referred to as a sample-and-hold image (SHS) signal value). The image bit level and the reset level are then correlated to provide the CDS readout value for that pixel. This CDS readout approach cancels out the kt/c associated with reset operations, which is otherwise dominant in low light.
In order to achieve optimal performance using the additional storage node approach, the MN must be optimized such that all the captured charge is transferred to the FD during CDS readout. That is, the two transfer gates and MN must be operably controlled to affect full charge transfer of the captured charge from the first pinned diode to the MN, and to affect the subsequent full charge transfer of the stored charge from the MN to the FD. In addition, the transfer gates must cooperate to effect good shutter performance of the MN (i.e., such that the MN exhibits low leakage, meaning low generation/recombination rates both in the dark and in the light).
The conventional additional storage node approach mentioned above fails to achieve optimal performance for several reasons. First, similar to the general 5T GS pixel approach (described above), captured charges are stored in the MN during the RS readout process (i.e., the captured charges are transferred to the FD only in the selected row), which subjects the captured charges to delay effects (generation) similar to those encountered in the general 5T GS pixel approach, although the applied parasitic generation current is arguably reduced over that encountered in the general 5T GS pixel approach by use of the pinned MN. Second, energy barriers for electrons prevent the full charge transfer from the pinned photodiode to the MN, and from the and MN to FD, which gives rise to image artifacts including image lag (i.e., when electrons that remain in the pinned diode or the MN are read at the next GS operation as an unwanted signal, and can be especially pronounced if the pixel collected photons from a bright source in the current GS operation). In order to operate correctly, there should be a built in potential difference between the pinned photodiode and the pinned memory node, but this potential difference is very difficult to achieve using the conventional power supply typically available in present-day CMOS process technologies (i.e., 0.18 micron process flows or smaller). For example, using a 0.18 micron CMOS process technology providing a 3.3V power supply, the inventors usually set the pinned photodiode to the maximum potential of about 1.5V and the FD/MN to about 3V to ensure a swing of about 1.5V before charge sharing in “high light” exposures and very good transfer in “low light” exposures. If is approach is applied to pixels of the conventional additional storage node approach, the pinned photodiode would require a maximum potential of 1.5V, the pinned MN diode would require 3V, and the FD would require 4.5V, which cannot be supported with the available 3.3V power supply. Further, even if an elevated supply voltage were available, there would still a problem to implement the MN pinned diode with the high maximum potential. Besides the design overhead when using higher voltages, additional problems can be anticipated. For example, supplying 4.5V from a charge pump is not a good solution because, at higher voltages, the generation current (electron generation rate) in the MN would be higher, and parasitic signals would appear, especially for the rows that are read out last. Thus, low light pixels read from rows at the end of a frame may appear erroneously brighter. Another problem with the conventional additional storage node approach mentioned above is that this approach suggests a p-shield, which actually increases the Vt in a part of the first transfer transistor, thus creating an additional potential barrier during electron transfer.
Various other prior art approaches attempt to achieve low-noise, full-charge-readout GS operations, but all of these prior art approaches also encounter problems. One prior art approach that attempts to modify noise reduction in GS pixels (such as those mentioned above) in order to achieve full-charge-readout is to enhance the lateral field in the transfer gate channel region. Various methods to create such a field have been investigated. For example, Boron implantation at the edge facing the photodiode was attempted, but was proven to be inefficient because the doping profile was deep and barrier lowering for electrons was difficult to achieve. Another approach taught in U.S. Pat. No. 7,825,444 to H. Rhodes (2010) includes an image sensor pixel includes indium doping in the source side of the transfer gate to generate a lateral doping profile, but the approach causes increased Vt, which in turn requires increased pixel operating voltages. Another prior art approach taught in U.S. Pat. No. 8,089,036 to Manabe et al (2012) provides an image sensor with global shutter and in-pixel storage transistor that utilizes 8T GS pixels and a CCD operation principle to possibility reduce voltage at the MN, but this approach requires two additional lines and two additional gates in comparison to the solution presented below.
What is needed is a CMOS image sensor that supports GS image capture, utilizes low-noise CDS readout operations, and facilitates decreased image distortion effects (i.e., by generation or recombination of charge in the process of the readout from first and last rows) than that of conventional approaches.